Chapter 2: Digital Logic and Microprocessor¶
Syllabus: AExE02
Coverage: AExE0201 through AExE0206
Status: DRAFT - syllabus and assigned-question pass complete; independent source audit pending
Exam use: Recognition of logic forms, binary arithmetic, processor organization, interfacing, and interrupt flow for recall/concept/light-calculation MCQs
Chapter map¶
| Code | Area | Highest-yield recognition cues |
|---|---|---|
AExE0201 |
Digital logic | radix conversion, complements, SOP/POS, K-map grouping |
AExE0202 |
Combinational and arithmetic circuits | MUX/DEMUX, decoder/encoder, adder/subtractor, signed overflow |
AExE0203 |
Sequential logic circuit | flip-flop triggering, registers, shift functions, sync vs async counters |
AExE0204 |
Microprocessor | ALU/CU/registers, buses, instruction cycle, assembly mnemonics |
AExE0205 |
Microprocessor system | memory hierarchy, PPI, serial/parallel transfer, DMA modes |
AExE0206 |
Interrupt operations | vectored vs non-vectored, ISR steps, masking, latency, priority |
Chapter rapid-revision sheet¶
| Trigger phrase | Immediate association |
|---|---|
| "group 4 binary bits" | one hex digit |
| "invert and add 1" | 2's complement |
| "non-weighted decimal code" | Excess-3 |
| "rows with output 1" | canonical SOP / minterms |
| "universal gate" | NAND or NOR |
| "data selector" | multiplexer |
| "code expander" | decoder |
| "sum bit" | XOR |
| "same-sign add gives opposite sign" | signed overflow |
| "stores one bit" | flip-flop |
| "serial to parallel" | SIPO register |
| "ripple delay" | asynchronous counter |
| "common clock to all stages" | synchronous counter |
| "next instruction address" | PC |
| "literal inside instruction" | immediate addressing |
| "8255 style programmable ports" | PPI |
| "start and stop bits" | asynchronous serial |
| "bulk transfer with little CPU service" | DMA |
| "save state, service event, restore state" | ISR flow |
Assigned-question audit¶
The chapter was checked against set1-007 to set1-012 and set1-065 to set1-068. Each row records the fact that decides the assigned item; question wording and keys are evidence, not technical authority.
| Target | Deciding fact | Result |
|---|---|---|
set1-007 |
canonical SOP is an OR of minterms | Supported by AExE0201 |
set1-008 |
discard the final carry-out in fixed-width 2's complement addition; test signed overflow separately | Supported by AExE0202 |
set1-009 |
conventional positive-pulse master-slave JK: master HIGH, slave LOW; polarity-specific qualification applies | Supported by AExE0203 |
set1-010 |
the control bus carries control/status signals, not operand data or device addresses | Supported by AExE0204 |
set1-011 |
DMA transfers directly between an I/O module and main memory | Supported by AExE0205 |
set1-012 |
simultaneous requests require interrupt-priority arbitration | Supported by AExE0206 |
set1-065 |
Excess-3 is non-weighted; 8421 BCD and 2421 are weighted decimal codes | Supported by AExE0201 |
set1-066 |
complement subtraction reuses an adder circuit | Supported by AExE0201/AExE0202 |
set1-067 |
master-slave operation prevents race-around | Supported by AExE0203 |
set1-068 |
a vector permits direct/table dispatch and can avoid a software source search | Supported by AExE0206 |
All ten assigned Chapter 2 items now have one technically defensible answer and an explicit deciding fact in the notes.
Sources and verification note¶
Primary authority for coverage is syllab.md. Technical facts were condensed from standard digital-design and microprocessor references rather than model keys.
Recommended verification sources for the pending independent audit:
- M. Morris Mano and Michael D. Ciletti, Digital Design - number systems, Boolean algebra, combinational circuits, flip-flops, registers, counters, and K-maps.
- Thomas L. Floyd, Digital Fundamentals - gate behavior, arithmetic circuits, code conversion, registers, and counter recognition cues.
- Ramesh S. Gaonkar, Microprocessor Architecture, Programming, and Applications with the 8085 - classical microprocessor architecture, buses, instruction cycle, assembly concepts, interfacing, DMA, and interrupts.
- Douglas V. Hall, Microprocessors and Interfacing - PPI, serial/parallel interfacing, memory/I-O concepts, and DMA controller behavior.
- Intel classical processor-family manuals for device-specific architecture examples; exact mnemonic sets remain processor-dependent.
This chapter is a review-oriented first edition, not a claim of exhaustive line-by-line verification against every processor family. When an exam stem becomes architecture-specific, the family being assumed must be inferred from context.