ACtE0406 Hardware description language and IC technology¶

IC-technology recognition¶

An integrated circuit fabricates many interconnected devices on one substrate. Useful exam classifications are independent axes:

• CMOS uses complementary NMOS and PMOS devices and is dominant in dense digital ICs because static power is ideally very low, although switching and leakage power remain.
• Bipolar technology can provide strong transconductance and speed but generally uses more static power than CMOS logic.
• BiCMOS combines CMOS density/control with bipolar drive or analog performance.
• FPGA configuration is field-programmable; an ASIC is fabricated for a specific application and is not field-reconfigured in the same sense.
• Do not attach universal transistor-count boundaries to SSI/MSI/LSI/VLSI unless the question states the convention used.

VHDL overview¶

VHDL is a hardware description language for modeling, simulating, and synthesizing digital systems.

Key recognition facts:

• hardware descriptions are concurrent at architecture level;
• VHDL is not a sequential programming language in the same sense as C, even though processes contain sequential statements;
• simulation semantics and synthesis realizability must be distinguished.

Entity, architecture, signal, variable¶

A generic is an entity parameter fixed during elaboration. It can parameterize widths, counts, and simulation timing constants. Static generic values may change elaborated structure through declarations or generate statements; they do not reconfigure structure dynamically at run time.

Minimal shape:

entity and2 is
    port(a, b : in std_logic;
         y    : out std_logic);
end entity;

architecture rtl of and2 is
begin
    y <= a and b;
end architecture;

Data representation and overflow using VHDL¶

Common logic/numeric types:

Validity condition:

• arithmetic meaning comes from type and package use, commonly numeric_std;
• std_logic_vector by itself is just a bit collection, not automatically a number.

Overflow cues:

• unsigned overflow wraps modulo \(2^n\) in fixed-width arithmetic unless extra bits/saturation logic are explicitly added;
• signed overflow occurs when result exceeds representable signed range;
• simulation may show wraparound behavior while system requirements may demand explicit overflow detection.

Design of combinational logic using VHDL¶

Common styles:

• concurrent signal assignment;
• combinational process with complete sensitivity list and complete assignments;
• selected or conditional signal assignment.

Combinational-process trap:

• incomplete assignment paths infer latches;
• missing inputs from sensitivity list cause simulation mismatch in older styles.

Design of sequential logic using VHDL¶

Clocked process template cue:

process(clk)
begin
    if rising_edge(clk) then
        q <= d;
    end if;
end process;

Recognition:

• edge test implies flip-flop/register inference;
• asynchronous reset is coded explicitly in sensitivity list and conditional structure if required;
• synchronous reset is tested inside clock-edge block.

Pipelining using VHDL¶

Pipeline in HDL means inserting registers between combinational stages.

Effects:

• increases throughput and maximum clock rate potential;
• increases latency in cycles;
• requires valid-data alignment/control handling.

Recognition cue: one stage per clocked register boundary.

HDL and IC-technology practical distinctions¶

• synthesis converts RTL-style VHDL into gate-level hardware implementation;
• simulation checks functional/timing behavior;
• not every legal VHDL construct is synthesizable;
• HDL describes digital IC behavior/structure; semiconductor fabrication technology is a separate physical layer concern.

VHDL revision box¶

• Entity = interface; architecture = implementation.
• Signal updates model hardware timing; variables update immediately inside a process.
• Use signed/unsigned with proper packages for arithmetic meaning.
• Incomplete combinational assignments infer latches.
• rising_edge(clk) implies sequential storage.
• Pipeline registers raise throughput but also add latency.