ACtE0403 Input-output organization and multiprocessor¶
Peripheral devices and I/O modules¶
Peripherals are external or support devices such as keyboard, display, printer, disk, ADC, DAC, timer, and communication interfaces.
I/O module roles:
- control and timing;
- processor communication;
- device communication;
- buffering;
- error detection/reporting.
Input-output interface and modes of transfer¶
An I/O interface adapts system-bus transactions to a peripheral. It commonly contains data, status, and control registers plus buffering and handshake/timing logic. Interfaces may be memory-mapped, sharing the processor address space, or isolated/port-mapped, using a separate I/O address space and instructions.
Three standard transfer modes:
| Mode | Recognition |
|---|---|
| Programmed I/O | CPU polls status and moves each word |
| Interrupt-driven I/O | device signals readiness/completion; CPU services via ISR |
| DMA | controller moves block directly between device and memory |
Tradeoff summary:
- programmed I/O is simplest but CPU-intensive;
- interrupt I/O improves responsiveness for intermittent events;
- DMA is best for large/high-rate transfers.
DMA details and validity conditions¶
DMA is useful when:
- transfer size is substantial;
- peripheral rate is high;
- CPU should be free for other work.
DMA is less beneficial when transfers are tiny or infrequent compared with setup cost.
Bus-arbitration recognition cues:
- DMA must obtain control of bus or memory path;
- cycle stealing steals bus cycles from CPU;
- burst mode can pause CPU memory activity for a block.
Multiprocessor characteristics¶
Multiprocessor = system with more than one processor cooperating within one overall computer system.
Characteristics commonly tested:
- higher throughput;
- potential parallel speedup;
- need for synchronization and communication;
- increased design complexity;
- memory consistency and contention issues.
Interconnection structure¶
| Structure | Recognition |
|---|---|
| Shared bus | simple, low cost, can bottleneck |
| Crossbar switch | many simultaneous paths, costly |
| Multistage network | scalable compromise |
| Point-to-point links | direct processor or node connections |
Uniform-memory-access versus non-uniform-memory-access cues may appear in advanced wording, but the syllabus mainly needs the idea that interconnect choice affects scalability, latency, and contention.
Inter-processor communication and synchronization¶
Communication methods:
- shared memory with synchronization primitives;
- message passing;
- interrupt or signal style notifications.
Synchronization methods:
- locks / mutexes;
- semaphores;
- barriers;
- atomic read-modify-write operations.
Recognition traps:
- communication moves information; synchronization coordinates safe ordering/access;
- a race condition occurs when outcome depends on uncontrolled timing of concurrent accesses.
I/O-multiprocessor revision box¶
- Programmed I/O polls; interrupt I/O reacts; DMA bulk-transfers.
- I/O modules buffer, control timing, and mediate between CPU and device.
- DMA reduces CPU data-move overhead.
- Multiprocessors need interconnect plus synchronization.
- Shared bus is simple but bottleneck-prone.
- Communication and synchronization are related but different problems.