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AExE0203 Sequential logic circuit

Sequential logic versus combinational logic

  • Combinational output depends only on present inputs.
  • Sequential output depends on present inputs and stored state.
  • Memory is commonly realized using latches, flip-flops, or registers.

Latches and flip-flops

Element Triggering style Recognition cue
Latch level-sensitive responds while enable is active
Flip-flop edge-triggered updates only on clock edge

The syllabus names RS flip-flops, gated flip-flops, edge-triggered flip-flops, and master-slave flip-flops. These fit the broader family below.

RS, D, JK, and T behavior

Device Main next-state idea Trap
RS latch / FF set, reset, hold forbidden condition in basic form
D FF next state follows D at active edge simplest storage element
JK FF refined RS; toggle when \(J=K=1\) race-around concern in level triggering
T FF toggles when T is 1 useful for counters

Basic RS meanings:

  • S = 1, R = 0 -> set;
  • S = 0, R = 1 -> reset;
  • S = 0, R = 0 -> hold for NOR-based RS latch;
  • S = 1, R = 1 is forbidden for the basic NOR latch.

Gated or clocked versions allow state changes only when the gate/clock condition is active.

Edge-triggered and master-slave operation

  • Edge-triggered flip-flops sample input only at the transition edge.
  • Positive-edge devices respond on the rising edge.
  • Negative-edge devices respond on the falling edge.
  • Master-slave flip-flops use two stages with opposite clock phases to prevent direct transparency.
  • In the conventional positive-pulse master-slave JK arrangement, the master is enabled while the clock is HIGH and the slave while it is LOW. Other polarity implementations can reverse these levels; opposite, non-overlapping phases are the invariant.

Race-around cue:

  • a level-triggered JK flip-flop can toggle repeatedly during one clock pulse when \(J=K=1\) and the pulse width is too large;
  • edge-triggered or master-slave realization removes that practical problem.

Registers

Register = a group of flip-flops used to store multi-bit data.

Types:

Type Function
SISO serial in, serial out
SIPO serial in, parallel out
PISO parallel in, serial out
PIPO parallel in, parallel out
Universal shift register can shift left, shift right, load, and hold

Applications of shift registers:

  • serial-to-parallel conversion;
  • parallel-to-serial conversion;
  • temporary storage;
  • digital delay line;
  • sequence generation and ring/Johnson counters.

Counters

Counter type Clocking Recognition
Asynchronous or ripple output of one FF clocks the next simple, slower due to ripple delay
Synchronous common clock to all FFs faster, better controlled timing

Key facts:

  • an \(n\)-flip-flop binary counter has modulus up to \(2^n\);
  • ripple counters accumulate propagation delay stage by stage;
  • synchronous counters need more combinational logic but reduce cumulative delay.

Ring and Johnson cues:

  • ring counter circulates a single 1 or 0;
  • Johnson counter feeds inverted last stage output back to first stage, giving up to \(2n\) states with \(n\) flip-flops.

Timing and state recognition

MCQ cues:

  • "stores one bit" -> flip-flop;
  • "samples only on rising edge" -> positive-edge-triggered FF;
  • "convert serial stream to byte" -> SIPO register;
  • "faster counter for high-speed logic" -> synchronous counter.

Sequential-logic traps

  • "gated" does not automatically mean edge-triggered.
  • The forbidden state depends on the exact RS implementation form.
  • A register stores multiple bits; a single flip-flop stores one bit.
  • Counter modulus is about the number of distinct states, not just the number of flip-flops.

Sequential-logic revision box

  • Latch is level-sensitive; flip-flop is edge-triggered in the usual exam sense.
  • JK with \(J=K=1\) toggles.
  • Master-slave and edge-triggered forms avoid race-around behavior.
  • Register = group of flip-flops.
  • Ripple counter is simpler but slower; synchronous counter is faster.
  • \(n\) binary flip-flops can represent up to \(2^n\) states.