ACtE0401 Control and central processing units¶
CPU structure and function¶
CPU core roles:
| Unit | Main job |
|---|---|
| ALU | arithmetic, logic, shift, compare |
| Control unit | sequencing and generation of control signals |
| Register set | fast working storage |
| Internal buses / datapath | move operands and results between units |
CPU function is usually described by the fetch-decode-execute cycle plus write-back and status update.
Computer configuration and datapath view¶
A classical computer system is CPU + memory + I/O connected by interconnects/buses.
Recognition cues:
- von Neumann style: instructions and data share memory and often a common path;
- Harvard style: separate instruction and data paths/memories;
- many embedded systems use modified Harvard compromises.
"Computer configuration" in exam wording often means how processor, memory, I/O, and buses are arranged and interact.
Control unit design¶
Two broad control approaches:
| Type | Recognition | Strength | Tradeoff |
|---|---|---|---|
| Hardwired control | combinational/sequential logic directly generates control | fast | harder to modify |
| Microprogrammed control | control signals encoded in control memory words | flexible, easier to extend complex instruction sets | usually slower than hardwired |
Control memory, microinstruction format, and sequencing¶
Control memory stores microinstructions for a microprogrammed control unit. It is a control store, not ordinary user program memory.
Key terms:
| Term | Meaning |
|---|---|
| Control memory / control store | storage containing microinstructions |
| Microinstruction | low-level control word that activates datapath operations |
| Microprogram | sequence of microinstructions implementing one machine instruction |
| Sequencer | selects next microinstruction address |
Microinstruction format often includes:
- control field(s) to enable transfers/ALU functions;
- condition field(s) for branching on status;
- next-address or sequencing information.
Horizontal versus vertical microcode cue:
- horizontal microinstruction: wide word, many directly encoded control bits, high parallelism;
- vertical microinstruction: more encoded/compact fields, less direct parallelism.
Addressing and sequencing¶
The syllabus phrase "addressing sequencing" belongs to control sequencing, not only operand addressing.
Possible next-microinstruction sources:
- sequential increment;
- branch on condition;
- mapping from opcode;
- subroutine return address in microprogramming.
Instruction formats and addressing modes¶
| Topic | Recognition cue |
|---|---|
| Instruction format | layout of opcode, register fields, immediate field, address/displacement |
| Addressing mode | rule for locating operand |
Typical operand-addressing modes:
- immediate;
- register;
- direct;
- indirect;
- indexed or base-plus-offset;
- relative;
- implied.
Instruction formats affect code density, decode complexity, and operand flexibility.
Data transfer and manipulation¶
Data-transfer operations include move, load, store, push, pop, exchange, and I/O transfer. Manipulation includes arithmetic, logical, shift, rotate, compare, and bit-set/clear operations.
Recognition trap: compare usually updates flags without storing an arithmetic result.
RISC and CISC with validity conditions¶
| Feature tendency | RISC tendency | CISC tendency |
|---|---|---|
| Instruction complexity | simpler | more complex |
| Instruction length | often fixed | often variable |
| Memory access model | load/store emphasis | memory-to-memory instructions may exist |
| Control implementation | often hardwired | often microprogrammed historically |
| Register count | usually larger | historically smaller/moderate |
Validity condition:
- these are tendencies, not absolute laws;
- modern CPUs blend features, so "RISC" and "CISC" are architectural styles, not strict binary categories.
Important suspect-key note:
- complex instructions in a CISC design are not defined by being "stored in CMOS";
- if microprogrammed, their control sequencing is conceptually stored in control memory/control store;
- CMOS is a semiconductor technology family, not the defining storage concept for the CISC-vs-RISC distinction.
Pipelining and parallel processing¶
Pipeline idea: overlap stages of multiple instructions.
Common stages:
- instruction fetch;
- decode / register fetch;
- execute;
- memory access;
- write-back.
Hazards:
| Hazard | Meaning |
|---|---|
| Structural | hardware resource conflict |
| Data | dependency between instructions |
| Control | branch/exception changes flow |
Parallel processing cue:
- can mean instruction-level, data-level, thread-level, or processor-level parallelism;
- pipelining increases throughput, not necessarily single-instruction latency.
CPU-control revision box¶
- ALU computes; control unit sequences; registers hold fast state.
- Hardwired control is fast; microprogrammed control is flexible.
- Control memory stores microinstructions in a microprogrammed unit.
- RISC/CISC are style tendencies, not perfect opposites in every modern CPU.
- CISC is not "complex instructions stored in CMOS."
- Pipeline improves throughput by overlapping stages.