AExE0206 Interrupt operations¶
Interrupt idea¶
An interrupt is an event that temporarily diverts CPU execution from the current program to a service routine.
Why interrupts matter:
- faster response to external or internal events;
- avoids wasteful polling loops in many cases;
- supports time-critical I-O and system control.
ISR and interrupt processing flow¶
Interrupt service routine (ISR) = special routine that handles the event and then returns control to the interrupted program.
Generic sequence:
- Interrupt request occurs.
- CPU completes the current instruction or reaches a defined interrupt boundary.
- CPU acknowledges interrupt if enabled and of sufficient priority.
- Context is saved fully or partly by hardware/software.
- ISR entry address is obtained.
- ISR executes service code.
- Context is restored.
- Return-from-interrupt resumes the interrupted program.
Interrupt classifications¶
| Type pair | Distinction |
|---|---|
| Hardware / software | external device request vs instruction-generated request |
| Maskable / non-maskable | can be disabled vs cannot normally be disabled |
| Vectored / non-vectored | fixed address, vector number, or hardware-supplied vector permits direct/table dispatch vs common dispatch code normally identifies the source |
| Synchronous / asynchronous | tied to instruction execution condition vs independent external timing |
Examples of synchronous events: trap, divide error, invalid opcode. Examples of asynchronous events: keyboard input, timer tick, device completion.
Priority, masking, and nesting¶
- If multiple interrupts occur, a priority scheme decides service order.
- Masking lets software disable selected interrupt sources.
- Non-maskable interrupts are reserved for urgent or fault conditions.
- Nested interrupts allow a higher-priority ISR to interrupt a lower-priority ISR if the system permits it.
Simultaneous-request priority arbitration decides which pending source is served first. It is distinct from interrupt nesting, in which a new interrupt preempts an ISR already running.
Recognition cue: priority encoder ideas often appear in interrupt hardware discussion.
Polling versus interrupts¶
| Method | Strength | Weakness |
|---|---|---|
| Polling | simple, deterministic check order | CPU time wasted when no event occurs |
| Interrupt-driven | efficient response to sporadic events | needs hardware/software support and context handling |
Interrupts are not automatically superior in every case. For very simple or predictable low-rate devices, polling may be acceptable.
Latency and service time¶
| Term | Meaning |
|---|---|
| Interrupt latency | time from request to start of ISR service |
| Service time | time spent handling the interrupt |
| Response time | total time until useful effect is produced |
Latency depends on:
- current instruction length/non-interruptible section;
- disabled interrupt windows;
- priority arbitration;
- context-save overhead.
Common traps¶
- ISR is not the interrupt signal itself; it is the routine that handles it.
- Return from subroutine and return from interrupt may differ because interrupt return must restore saved status/state correctly.
- Maskable does not mean low priority by definition, only disable-able.
- Vectored dispatch often reduces software source-search work, but it is not universally faster and the device need not supply a complete ISR address.
Interrupt revision box¶
- Interrupt temporarily diverts control to an ISR.
- Generic ISR flow: acknowledge, save context, service, restore, return.
- Maskable can be disabled; non-maskable normally cannot.
- Vectored means a fixed address or supplied vector enables direct/table dispatch.
- Polling checks continuously; interrupts react on request.
- Latency is the delay before service begins.