Skip to content

AExE0205 Microprocessor system

Memory classification and hierarchy

Memory is classified by speed, capacity, volatility, and proximity to the CPU.

Level Speed Capacity Typical role
Registers fastest smallest current operands/state
Cache very fast small bridge between CPU and main memory
Main memory (RAM) fast moderate active program/data storage
Secondary storage slower large long-term storage

Volatility cue:

  • RAM is usually volatile;
  • ROM/flash are non-volatile;
  • non-volatile does not mean writable at normal CPU speed.

Memory devices and hierarchy terms

Device class Core property
ROM non-volatile read-mostly storage
PROM programmable once after manufacture
EPROM erasable with UV light
EEPROM electrically erasable
Flash block-erasable EEPROM family
SRAM fast, no refresh, lower density
DRAM high density, needs refresh

Recognition traps:

  • SRAM uses flip-flop-like cells, so it is faster but larger and costlier per bit.
  • DRAM uses capacitive storage and periodic refresh.

Memory and I-O interfacing

Interfacing means selecting the right device and connecting it to processor buses and control signals.

Typical signals:

  • address lines for location/device selection;
  • data lines for transfer;
  • read/write control;
  • chip-select or enable;
  • ready/wait signals in slower systems.

Memory-mapped versus isolated I-O:

Method Recognition cue
Memory-mapped I-O peripherals occupy address space and use normal memory instructions
Isolated or port-mapped I-O separate I-O address space and special I/O instructions

The exact choice depends on processor architecture.

Parallel interface and PPI

Parallel transfer sends multiple bits simultaneously across multiple lines.

Introduction to PPI:

  • a programmable peripheral interface is a configurable parallel I-O chip;
  • the 8255 PPI is the classic exam example;
  • it typically provides ports A, B, and C;
  • ports can be programmed for input, output, or handshaking modes depending on the device.

Recognition cue: when a question mentions programmable 8-bit ports with control-word configuration, think PPI/8255 family behavior.

Serial interface and transmission mode

Serial transfer sends bits one after another over fewer lines.

Type Clocking Recognition
Synchronous serial shared clock or embedded timing high rate, coordinated clocking
Asynchronous serial no shared clock line; start/stop bits frame characters UART/RS-232 style

Asynchronous character frame cue:

  • start bit;
  • data bits;
  • optional parity;
  • stop bit(s).

Serial interface standards commonly cited:

Standard Core idea
RS-232 point-to-point, single-ended, classic asynchronous serial
RS-422 differential signaling, longer distance
RS-485 differential multi-drop bus
SPI synchronous, master-slave, short-distance board-level
I2C synchronous 2-wire bus with addressing

DMA and DMA controllers

Direct memory access allows data transfer between I-O and memory with limited CPU intervention.

DMA sequence:

  1. CPU initializes DMA controller with source, destination, count, and mode.
  2. Device requests transfer.
  3. DMA controller arbitrates for bus control.
  4. Data moves between device and memory.
  5. Controller reports completion, often by interrupt.

DMA advantages:

  • reduces CPU overhead for bulk transfer;
  • useful for disks, ADC streams, network transfer, high-rate peripherals.

Common DMA modes:

Mode Recognition
Burst / block controller keeps bus for a block transfer
Cycle stealing controller takes one bus cycle at a time
Transparent transfer during CPU-idle bus periods

Validity condition: DMA helps when transfer volume is large enough to justify setup overhead.

Microprocessor-system revision box

  • Registers < cache < RAM < secondary storage in speed order.
  • SRAM is faster and no-refresh; DRAM is denser and refreshed.
  • Memory-mapped I-O uses normal address space; isolated I-O uses separate port space.
  • Parallel transfer uses many lines; serial transfer uses fewer lines over time.
  • Asynchronous serial uses start/stop framing.
  • DMA moves blocks with much less CPU servicing than programmed I-O.