Chapter 4: Computer Organization and Embedded System¶
Syllabus: ACtE04
Coverage: ACtE0401 through ACtE0406
Status: DRAFT - syllabus and assigned-question pass complete; independent source audit pending
Exam use: Recognition of CPU/control-unit structure, cache and memory rules, I/O and multiprocessor concepts, embedded-system tradeoffs, RTOS/control facts, and VHDL design cues for recall/concept/light-calculation MCQs
Chapter map¶
| Code | Area | Highest-yield recognition cues |
|---|---|---|
ACtE0401 |
Control and central processing units | control memory, addressing sequencing, ALU, RISC/CISC, pipeline |
ACtE0402 |
Computer arithmetic and memory system | hierarchy, cache mapping, replacement, write policy, volatility |
ACtE0403 |
Input-output organization and multiprocessor | programmed I/O, interrupt I/O, DMA, interconnect, synchronization |
ACtE0404 |
Hardware-software design issues on embedded system | classification, custom processor, ASIP, development environment |
ACtE0405 |
Real-time operating and control system | task/process/thread, scheduling, synchronization, open vs closed loop |
ACtE0406 |
Hardware description language and IC technology | VHDL entity/architecture, data types, overflow, sequential/combinational, pipeline |
Chapter rapid-revision sheet¶
| Trigger phrase | Immediate association |
|---|---|
| "control store" | control memory for microinstructions |
| "hardwired vs microprogrammed" | speed vs flexibility tradeoff |
| "complex instruction set stored in CMOS" | suspect wording; correct concept is control-memory / architectural style, not CMOS |
| "load/store style" | RISC tendency |
| "overlap fetch and execute stages" | pipelining |
| "hit ratio" | fraction of cache accesses found locally |
| "one block to exactly one line" | direct-mapped cache |
| "dirty block" | write-back cache concept |
| "bulk transfer without CPU moving each word" | DMA |
| "shared bus bottleneck" | simple multiprocessor interconnect |
| "dedicated system in product" | embedded system |
| "middle ground between CPU and ASIC" | ASIP |
| "deadline miss unacceptable" | hard real-time |
| "feedback used to correct output" | closed-loop control |
| "entity plus architecture" | VHDL structural unit |
| "bit vector without inherent numeric meaning" | std_logic_vector |
| "incomplete combinational process assignment" | unintended latch |
| "register between stages" | pipeline |
Assigned-question audit¶
The chapter was checked against set1-019 to set1-024 and set1-073 to set1-076. Each revised item has one technically valid answer and an explicit deciding fact.
| Target | Deciding fact | Result |
|---|---|---|
set1-019 |
microprogrammed implementations store microinstructions in control memory | Supported by ACtE0401 |
set1-020 |
“write within” is not standard write or write-miss policy terminology | Supported by ACtE0402 |
set1-021 |
cycle stealing is a DMA bus-transfer mode | Supported by ACtE0403 |
set1-022 |
algorithmic/behavioral level models the algorithm without gate/switch/circuit detail | Supported by ACtE0404 |
set1-023 |
VHDL generics parameterize an entity at elaboration | Supported by ACtE0406 |
set1-024 |
concurrent execution of multiple jobs in one system is multitasking | Supported by ACtE0405 |
set1-073 |
a microprogrammed control unit uses microinstructions in control memory | Supported by ACtE0401 |
set1-074 |
direct mapping assigns each memory block to one fixed cache line | Supported by ACtE0402 |
set1-075 |
DMA is efficient for large I/O-memory block transfers | Supported by ACtE0403 |
set1-076 |
an embedded system performs dedicated functions within a larger product or control environment | Supported by ACtE0404 |
Sources and verification note¶
Primary coverage authority is syllab.md. Technical content was aligned to standard computer-organization, embedded-system, RTOS, and VHDL references.
Recommended verification sources for the pending independent audit:
- William Stallings, Computer Organization and Architecture - CPU organization, control-unit design, instruction formats, addressing modes, cache hierarchy, I/O modes, and multiprocessors.
- M. Morris Mano, Computer System Architecture - microprogrammed control, ALU/datapath ideas, pipeline, and memory-system organization.
- David A. Patterson and John L. Hennessy, Computer Organization and Design - RISC/CISC tendencies, pipeline hazards, cache behavior, and performance tradeoffs.
- Frank Vahid and Tony Givargis, Embedded System Design - embedded classification, HW/SW partitioning, custom processors, and ASIP-style tradeoffs.
- Jane W. S. Liu, Real-Time Systems and common RTOS references - scheduling, synchronization, determinism, and control-oriented real-time behavior.
- IEEE 1076 VHDL language reference concepts and standard teaching texts such as Douglas Perry / Bhaskar - entity/architecture, signals vs variables, synthesizable combinational and sequential coding, and pipelining.
This chapter is a review-first edition. Claims that depend strongly on a specific processor, RTOS, or FPGA toolchain are stated as tendencies or context-dependent rules rather than universal absolutes.